1. Technical Field
Several aspects of the present invention relate to a method for manufacturing a semiconductor device, particularly to a method for forming an interconnection (conductive film) of a semiconductor device.
2. Related Art
Semiconductor devices have a multilayer structure including semiconductor films, insulating films, and conductive films. As the element size of semiconductor devices decreases, forming those semiconductor devices finer (i.e. narrower and thinner) is increasingly required.
Techniques using liquid material for forming components such as thin film transistors (TFTs) and interconnections of semiconductor elements on a glass substrate have been developed, so as to constitute a display unit or a drive unit of a display such as a liquid crystal device or an organic electroluminescence device.
For instance, a patterning method is disclosed in JP-A-2005-121181 the method including forming a bank (B) on a substrate (P) and depositing a functional fluid (L) on a region (A) partitioned by the bank (B), in order to form a thin linear pattern in a high precision. The numerals in the parentheses are quoted from the JP-A-2005-12181.
The inventor is engaged in research and development of semiconductor devices, studying the optimal method for forming, interconnections in the formation of circuits and the like that have semiconductor elements such as TFT.
His study includes not only a designing of the finer interconnections, but also an optimal method for forming the interconnections in order to achieve very small sized elements and highly integrated interconnections, since forming of interconnections in a multilayer structure is critical for such purposes.
If interconnections are deposited as a multilayer, parasitic capacitance is generated between the interconnections arranged one on top of the other, with an interlayer insulating film therebetween. Due to the parasitic capacitance, the rapid operation of the interconnections is disturbed. In order to reduce this parasitic capacitance, the measures may be taken, for instance, increasing the thickness of the interlayer insulating film, or using low-conductivity (low-k) materials for interlayer insulating film.
These measures, however, increase the film stress and generate cracking of the films, possibly resulting in a degradation of element characteristics such as interconnection between the films and TFTs. Particularly, film deposition on a large-sized substrate or a flexible substrate requires film stress reduction. Thus, measures other than the above is important for reducing the parasitic capacitance.
Moreover, capacitors (capacitance) are often incorporated into a display unit or a drive unit of the display device. In order to ensure a large capacitance in the capacitors, it is necessary to make the top-to-bottom distance of the interconnection (i.e., thickness of the insulating film) small. In order to increase the capacitance, it has been necessary to design the capacitor insulating film to be manufactured in a different process from that of the interlayer insulating film. At the same time, it has been necessary to compose the capacitor insulating film with a high-conductivity (high-k) material.